The storage of huge amount of information on computer systems becomes more and more important. Particularly, flash memory arrays may be employed for this purpose.
Two-transistor configurations in a memory cell with an access transistor and a memory transistor allow fast random access and low power program and erase by tunnelling.
FIG. 1 shows a conventional two-transistor configuration with a conventional floating gate memory cell 100.
In a silicon substrate 101, a source region 102, a source and drain region 103 and a drain region 104 are provided as highly doped portions. An access transistor 110 comprises a gate oxide layer 111, an access gate 112, an interpolydielectric (IPD) layer 113, a contact structure 114 and a polysilicon structure 115. Furthermore, a memory transistor 120 is provided which comprises a tunnel oxide layer 111, a floating gate 121, an interpolydielectric layer 113 and a control gate 122.
Thus, FIG. 1 shows a transistor configuration in which the memory transistor 120 is implemented with a floating gate 121. Typically, the gate oxide 111 is approximately 8 nm thick. The memory transistor 120 stores the information (charge) in the floating gate 121. Both tunnel oxide 111 and interpolydielectric 113 layer are thicker than 8 mm due to retention issues.
According to another conventional two-transistor memory architecture which is shown as a memory cell 200 in FIG. 2, an access transistor 210 is provided as well as a memory transistor 220. As a charge carrier storage structure, the memory transistor 220 includes an ONO layer 221, that is a silicon oxide-silicon nitride-silicon oxide layer sequence.
FIG. 2 shows a so-called SONOS memory cell 200 (semiconductor-silicon oxide-silicon nitride-silicon oxide-semiconductor).
The access transistor 110, 210 (basically a MOSFET) which acts like a switch contributes to the selection/inhibition of a memory transistor 120, 220 in a memory array comprising a large number of memory cells 100, 200. The use of an access transistor 110, 210 allows the memory 100, 200 to be fully programmed and erased by Fowler-Nordheim tunnelling and allows to operate the individual memory cells 100, 200 without disturbing cross talk. The memory transistor 120, 220 stores the information that is encoded in stored electric charge. This charge can be injected in a polysilicon floating gate layer 121, a nitride layer of the ONO layer 221, nano-crystal dots, etc.
FIG. 2 therefore illustrates a transistor configuration in which the memory transistor 220 is implemented as a SONOS sequence. In this case, both the access transistor 210 and the memory transistor 220 have a single poly layer 112, 122. The gate oxide 111 of the access transistor 210 has a thickness of approximately 8 nm. The memory transistor 220 stores the information (charge) in a nitride layer 230 of approximately 6 nm thickness and is sandwiched between two insulator (SiO2) layers, namely a bottom oxide 231 and a top oxide 232 of 2 nm and 8 nm thickness, respectively, whereas the three layers 230 to 232 form the ONO layer 221.
However, it is a problem that a standard planar flash memory cannot be scaled properly beyond 50 nm. Particularly, the scaling of tunnel and control dielectric thickness is limited by concerns for data-retention, yielding low coupling ratios and consequently high operating voltages. Moreover, one of the major limiting scaling parameters for two-transistor flash cells is the length of the access gate transistor 110, 210, which under worst case conditions (Fowler-Nordheim program inhibit) should have a leakage current not exceeding approximately 100 pA with as much as 5 V on its drain. These circumstances result in the fact that future scaled cells suffer of short channel effects and punch through phenomena, as well as of small on-current/off-current ratio, thus reducing the sensing margin.
A possible strategy is to increase the control of the gate over the channel with configurations such as double gate and FinFET transistors to increase the coupling efficiency between the control gate over the floating gate. Higher coupling is needed to scale down the programming voltages so as the memory cell dimensions. However, double gate and FinFET transistors are difficult in manufacture and operation.
US 2003/0015755 A1 discloses a vertical transistor, a memory arrangement and a method for fabricating a vertical transistor. Particularly, US 2003/0015755 A1 discloses a vertical transistor which has a source region, a drain region, a gate region, and a channel region between the source region and the drain region, which are arranged in a vertical direction in a semiconductor substrate, the gate region having an electrical insulation from the source region, from the drain region and from the channel region and being arranged around the channel region in such a way that the gate region and the channel region form a coaxial structure.
However, with the procedure of forming a memory arrangement according to US 2003/0015755 A1, it may be difficult to obtain a sufficient integration density of memory cells. Furthermore, the manufacturing procedure according to US 2003/0015755 A1 is difficult and cost intensive.